Generation and Implementation of Barker and Nested Binary codes

Recent advances in the development of semiconductors allow the realization of low cost hardware architecture for implementing Barker and Nested binary codes suitable for radar applications. Due to the fast development in Digital Signal Processors (DSP) they are used in radar signal processing. Radar signal processing is defined as exploitation of the received signal represented in digital form to extract the desired information while rejecting unwanted signals. DSP’s are used for implementing many of the radar applications. FPGA based implementation of Barker and Nested binary codes are presented and are suitable for real time applications. FPGA provides a reconfigurable solution for implementing DSP applications. Since FPGA’s can be reconfigured in hardware, FPGA’s offers complete hardware customization for implementing various pulse compression codes. The implementation of Barker and Nested binary codes utilizes the Linear Feedback Shift Registers [LFSR], exhaustive search method. The performance of these codes is given in terms of MeritFactor(MF). The performance measures are calculated offline on a host PC in Matlab for the codes generated by VHDL program. The synthesized binary sequences have good MF values compared with previous work in the literature.